Comparisons Between a Z80 and 8080 CPU

Below is a a detailed discussion about the differences between a Z80 and 8080 CPU as describe in the SD-Systems Z8800 Z80 manual. It is brief but well done. The instruction set of the Z-80 is divided into 8 groups. Different groups of instructions are discussed in turn.

Load and Exchange Group

The load instructions cause data to be transferred from a source location to a specified destination.  All load instructions must specify both a source and a destination.  No changes are made to the data source.  In every case except loading the accumulator from either the I or the R registers, the status flags are not modified.  In addition to the load instructions there are six exchange instructions.  Two of these exchange the HL register pair with either the DE register pair or the memory location pointed to by the SP register.  These two instructions are common to 8080A instruction set.  Two new exchange type instructions have been added to the Z-80 instruction set.  One type exchanges either the IX register or the IY register with the memory location specified by the SP register.  The second instruction type exchanges either the AF register pair with its alternate or the BC, DE and HL register pairs with their alternates.  This last instruction type is very valuable in fast context switch applications such as interrupt processing.  A final pair of instruction types are the PUSH and POP instructions.  These instructions allow the contents of any register pair to be copied onto or loaded from a downward growing stack.  These instructions are the same as those in the 8080A except that they are expanded to include the IX and IY registers.

Block Move and Block Search Group

The second instruction group, the block move and block search instructions, make up a totally new set of instructions.  This group of instructions provides the Z-80 with the most powerful set of string manipulation instructions available on any currently available microprocessor.  All instructions within this group use one or all of the following register pairs during execution.  The HL pair is the source location pointer; the DE pair is the destination location pointer; and the BC pair is the byte counter.  Four block move instructions are provided in the Z-80 instruction set:  LDI, LDIR, LDD, and LDDR.  The LDI instruction takes a byte of data from the source location and deposits it in the destination location.  The HL and DE register pairs are then incremented and the BC pair is decremented.  The LDIR instruction works in exactly the same manner except that instruction execution is repeated until BC is equal to zero.  The LDD and LDDR instructions work in analogous manners to the LDI and LDIR instructions except that the HL and DE register pairs are decremented rather than incremented.

 The block search instructions use the HL and BC register pairs just as they were used in the block move instructions.  The accumulator is used in the block search instructions to contain the match value.  The four instructions (CPI,CPIR,CPD,CPDR) cause the source byte to be compared with the data in the accumulator. The results of the comparison are stored in the zero status flag; the byte count is decremented and the HL register pair is incremented or decremented as the instruction indicates. If the BC register pair contains a zero after decrementing, the parity/overflow flag bit is set.  If the instruction is a repeat type instruction, the process is repeated until a match is found or the byte count is equal to zero. The block move and block search instructions are invaluable when large strings of data must be manipulated such as in a word pro­cessing system or an assembler.  All of these instructions are interruptible and therefore do not prevent the CPU from responding to interrupts in a timely manner.

Arithmetic and Logical Group

The third group of instructions, the arithmetic and logical instructions, are divided into three basic subgroups.  Subgroup one is the eight bit arithmetic and logical operations.  Subgroup two is the general purpose AF operations.  Subgroup three is the sixteen bit arithmetic operations.                                           

 The eight bit arithmetic and logical operations are essentially the same as those in the 8080A except that they are expanded to  include IX and IY register addressing.  All of these instructions except the INC and DEC instructions assume that the accumulator is one of the operands.  In all cases except INC, DEC, and CP, the accumulator receives the result of the operation and the appropriate status flags are modified.  The parity/overflow flag bit is a special case in that the parity indication is set by a logical operation and the overflow indication is set by an arithmetic operation.  The CP instruction modifies all flags as an arithmetic operation but the result is not stored in the accumulator. Both the INC and DEC instructions may use any register or memory location as a source/destination specification.  Both effect all flags except the carry flag.

The general purpose AF register pair operations are the same as those in the 8080A except for the addition of the NEG instruction and the modification of the DAA instruction to take into account a decimal adjust after a subtraction operation.  The NEG is an instruction not found in the 8080A.  It performs a single instruction two's complementing operation on the accumulator.  This replaces the complement and increment operations necessary in the 8080A.

 The sixteen bit arithmetic operations contain some new and very useful instructions.  The sixteen bit INC and DEC instructions operate in the same manner as the 8080A instructions but are expanded to include the IX and IY registers.  The ADD instruction with the HL register pair as the destination location is identical to the equivalent 8080A instruction.  The ADD instruction has been expanded to allow the IX and IY registers to act as destination locations. This expansion will allow the BC, DE, SP and either the IX or IY register pairs to be added to either IX or IY respectively.  This operation will effect only the carry flag.  In addition to the preceding instructions, the Z-80 has a sixteen bit ADC and a sixteen bit SBC instruction.  These instructions use the HL register pair as the destination location and use BC, DE, HL and SP as valid source locations.  All flags are modified by these instructions. These instructions greatly facilitate extended sixteen bit arith­metic operations.

Rotate and Shift

A powerful series of instructions are contained in the fourth instruction group.  In the 8080A, all rotates occurred with the accumulator as operand.  The Z-80 uses the same four rotate operations but allows any eight bit register or memory location to be directly manipulated.  For memory operations, the location is specified either by HL or by one of the index registers plus a displacement.  The Z-80 also contains a shift left operation and two shift right operations.  The shift operations use the same operands as the rotate instructions and provide a useful tool for a wide variety of applications.  Also unique to the Z-80 are two instructions which allow a BCD digit to be rotated out of or into a memory location to or from the less significant four bits of the accumulator.  This is a tremendous aid in BCD arithmetic.  The operand, specified by the HL register pair may be rotated either left or right.

 Bit Manipulation Group

The fifth instruction group, bit manipulation group, contains three instruction types.  These instruction types allow any bit located in any general purpose register or memory location to be set, reset or tested.  The zero flag records the result of a bit test.  No flags are effected by the set and reset operations.

 Jump, Call and Return Group

The sixth instruction group contains the jump, call and return instruction type.  All of the instructions within this group mani­pulate the sixteen bit PC register.  The jump instruction type may be either an unconditional or conditional jump.  The conditional jump tests the status of the carry, parity/overflow, zero and sign flags within the flag register. The jump instruction type uses one of three addressing modes. These modes (Absolute, Relative, or Register Indirect) allow for a choice of instruction types to meet any requirement.  The Absolute addressing mode of a jump instruction type loads the PC register with the two bytes of data immediately following the Opcode of the jump. This mode exists in the 8080A.

The Relative addressing mode for a jump type instruction is new in the Z-80.  This instruction is a two byte instruction in which the second byte is a signed two compliment displacement which is added to the PC register to form the new execution address. This addressing mode allows the most common types of jumps such as loops and conditional jumps around short blocks of code to be accomplished with two instead of three bytes of code. When using this instruction type, calculate all displacements from the start of the next instruction.  The relative addressing range is +129 to -126 bytes as measured from the jump instruction Opcode.  This instruction type is not found in the 8080A.

Register Indirect type of jump instruction causes the contents of the PC register to be unconditionally replaced by the contents of the HL register pair, IX or IY.  For table driven systems and other software applications in which the final execution address is calculated dynamically, this instruction type is essential.  This instruction type is an expansion of the original 8080A instruction equivalent.

A second member of this instruction group is the Call type instruction. A call instruction pushes the memory location of the instruction immediately following the CALL onto the stack and then branches to the specified address.  The Z-80 implements two types of Call instructions.  The first type is the RST instruction.  This one byte instruction allows a very convenient way to call commonly used subroutines such as I/O routines. The RST instruction causes execution control to be transferred to one of eight locations in the 64 byte memory. This instruction functions just as the equivalent instruction operates in the 8080A.

The second type of call instruction is the CALL.  CALL is a three byte instruction in which the second and third bytes specify the subroutine start address. The CALL instruction exists as either an unconditional or a conditional call just as in the case of the jump type instruction, these are found in the 8080A.

The last member of this instruction group is the return type instruction.  This is a single byte instruction and pops the return address from the top of the stack. Three types of return instructions are implemented on the Z-80. Two of these, RETI and RETN, are defined as a return from maskable interrupt and non­maskable interrupt routines respectively. These returns automa­tically re-enable interrupt processing so that a separate interrupt enable instruction is unnecessary.  These are not found in the 808OA.

The third type of return, RET, is a general purpose subroutine return and exists in both a conditional and unconditional form. This type of instruction is also found in the 8080A. 

Input/Output Group

The Z-80 has a considerably expanded set of I/O type instructions. In addition to the input and output instructions which use the accumulator as the data destination or source, the Z-80 has two additional I/O modes. The first mode takes the I/O port address from the C register and loads data into or out of any register except the C register. In the case of an input into the C register with the port address contained in the C register, only the flag register is effected. This allows flags to be tested without disturbing any register.  The register indirect I/O instructions are not found in the 8080A.

The second I/O mode is a block transfer type instruction. These instructions take the port address from the C register, the byte count from the B register and the destination/source address from the HL register pair. These block transfer instructions allow either incrementing memory addressing or decrementing memory addressing and also allow either repeat until the B register is equal to zero or no repeat. With this mode of instruction up to 256 bytes of data may be transferred with extreme ease.  The block transfer instructions are not found in the 8080A.

CPU Control Group

This instruction group contains those instructions which are used to establish the state of the CPU.  The NOP instruction effects no register and is used to delete an instruction or group of instructions without re-assembling the code.  It also is used to provide space for expansion of code.  The HALT instruction causes the CPU to begin executing internally generated NOP instruc­tions until the CPU is reset or until an interrupt request is received This instruction does not effect the memory refresh operations of the CPU.  The DI and EI instructions disable and enable respectively the maskable interrupt.

The final group of three instructions set up the interrupt response modes.  The Z-80 has three interrupt response modes.  The first mode, mode zero, allows the interrupting device to jam any instruc­tions onto the data bus and the CPU will execute it.  This mode is the default mode and is the same interrupt response as the 8080A.

Mode one is a simplified interrupt mode in which the CPU will automatically execute an RST to location 56 in response to an interrupt request.  This mode requires no special interrupt pro­cessing hardware external to the CPU.

The third mode, mode two, is the most powerful interrupt pro­cessing mode.  When an interrupt request is received, the CPU will accept an eight bit address from the interrupting device. These bits form the lower order bits of an interrupt vector table address.  The high order bits are taken from the I register. Once the CPU has formed this address, the contents of location pointed to by that address and the next location are loaded into the PC register after the current PC register contents are pushed onto the stack. This allows up to 128 interrupt processing routines to be directly addressed. This facility is the most powerful interrupt processing scheme currently available on any micro­processor.

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