X1 Memory Mapping (Size and Bank [2K in bank 3]) (2-3, 4-5, 6-7, 8-10, 9-10, 11-12) 1 A10 2 U11 (LS138) pin 1 3 A11 4 U11 (LS138) pin 2 5 A12 6 U11 (LS138) pin 3 7 A13 8 U10 (LS20) pin 2 9 A14 10 U10 (LS20) pin 4 11 A15 12 U10 (LS20) pin 5 13 A13\ 14 U10 (LS20) pin 1 15 A14\ 16 A15\ X2 ROM Type (3-4, 5-10, 7-?) 1 +5 2 +5 3 ROM pin 19 4 A10 5 ROM pin 18 6 A11 7 ROM pin 21 8 A12 9 GND 10 GND X3 Chip Selects (Location in selected bank - Drives Phantom) (9-10, 11-12, 13-14, 15-16) 1 Select 0 (U11 pin 15) 2 ROM 0 Low (CS\ ROM 0) 3 Select 1 (U11 pin 14) 4 ROM 1 Low (CS\ ROM 1) 5 Select 2 (U11 pin 13) 6 ROM 2 Low (CS\ ROM 2) 7 Select 3 (U11 pin 12) 8 ROM 3 Low (CS\ ROM 3) 9 Select 4 (U11 pin 11) 10 ROM 0 High (CS\ ROM 0) 11 Select 5 (U11 pin 10) 12 ROM 0 High (CS\ ROM 1) 13 Select 6 (U11 pin 9) 14 ROM 0 High (CS\ ROM 2) 15 Select 7 (U11 pin 7) 16 RAM High X4 Parallel Port 1 Positive True 2 J3-21 Output Strobe 3 Negative True 4 GND (Always Enabled) 5 Output Enable 6 J3-19 ORPLY* X5 PP Output Strobe Cleared By (SHORTED ORPLY*, OPEN Software) 1 2 X7 PP Input Latch 1 J3-22 ISTRB* 2 Input Port Latch 3 +5 (Always Enabled) X8 System Clock 1 4MHz 2 Clock Input (U21) 3 2MHz X10 RS-232 TXClock 1 1489 pin RS-232 RXCLK (DD) 2 USART TXC 3 CTC TO0 (Conditioned by U15) X11 RS-232 DSR\ (1 to 2 allows monitor to measure bit rate) (2-3) DTR 1 USART RXD 2 USART DSR\ 3 DTR (CD) X12 CTC Vectored Interrupts 1 2 3 8251-16 SYNC Detect 4 S100-8 VI4 5 CTC-20 TR3 6 8251-X TX Ready X13 CTC Vectored Interrupts 1 8251-X RX Ready 2 CTC-21 TR2 3 S100-7 VI3 X14 CTC Vectored Interrupts(3-4) 1 CTC-23 TR0 2 S100-5 VI1 3 CTC-22 TR1 4 S100-6 VI2 5 2MHz Clock X15 Auto Start/Interrupt Chain Out 1 2 3 S100-64 4 CTC-13 IEO X16 Auto Start 1 U22 (LS74) pin 9 2 U32 (LS32) pin 4 3 A13 X17 Auto Start 1 U22 (LS74) pin 9 2 U32 (LS32) pin 1 3 A15 X18 Auto Start (2-3) 1 U22 (LS74) pin 9 2 U32 (LS32) pin 13 3 A12 4 U22 (LS74) pin 9 5 U32 (LS32) pin 10 6 A14 0000 X17-2 to X17-3, X18-5 to X18-6, X16-2 to X16-3, X18-2 to X18-3 1000 X17-2 to X17-3, X18-5 to X18-6, X16-2 to X16-3, X18-1 to X18-2 2000 X17-2 to X17-3, X18-5 to X18-6, X16-1 to X16-2, X18-2 to X18-3 3000 X17-2 to X17-3, X18-5 to X18-6, X16-1 to X16-2, X18-1 to X18-2 4000 X17-2 to X17-3, X18-4 to X18-5, X16-2 to X16-3, X18-2 to X18-3 5000 X17-2 to X17-3, X18-4 to X18-5, X16-2 to X16-3, X18-1 to X18-2 6000 X17-2 to X17-3, X18-4 to X18-5, X16-1 to X16-2, X18-2 to X18-3 7000 X17-2 to X17-3, X18-4 to X18-5, X16-1 to X16-2, X18-1 to X18-2 8000 X17-1 to X17-2, X18-5 to X18-6, X16-2 to X16-3, X18-2 to X18-3 9000 X17-1 to X17-2, X18-5 to X18-6, X16-2 to X16-3, X18-1 to X18-2 A000 X17-1 to X17-2, X18-5 to X18-6, X16-1 to X16-2, X18-2 to X18-3 B000 X17-1 to X17-2, X18-5 to X18-6, X16-1 to X16-2, X18-1 to X18-2 C000 X17-1 to X17-2, X18-4 to X18-5, X16-2 to X16-3, X18-2 to X18-3 D000 X17-1 to X17-2, X18-4 to X18-5, X16-2 to X16-3, X18-1 to X18-2 E000 X17-1 to X17-2, X18-4 to X18-5, X16-1 to X16-2, X18-2 to X18-3 F000 X17-1 to X17-2, X18-4 to X18-5, X16-1 to X16-2, X18-1 to X18-2 X19 Interrupt Chain In 1 S100-14 2 CTC-13 IEI X20 RS-232 (Standard Etch is DCE 1-20, 2-19, 3&4-18, 5-16, 10-11) 1 USART TXD\ 2 USART RXD\ 3 USART RTS\ 4 USART CTS\ 5 USART DTR\ 6 USART DSR\ 7 USART TXC 8 USART RXC 9 RING DET (CE) 10 +12V 11 CDET (CF) 12 XCLK (DB) 13 RXCLK (DD) 14 TXCLK (DA) 15 DTR (CD) 16 DSR (CC) 17 RTS (CA) 18 CTS (CB) 19 TXD (BA) 20 RXD (BB) X21 USART Clock Source 1 1489 pin RS-232 RXCLK (DD) 2 USART RXC pin 25 3 CTC TO0 (Conditioned by U15) X22 DMA 1 CPU-23 BUSACK Disables Driver 2 Bus Drivers 3 S100-19 CDSB* Disables Driver