SECTION II THEORY OF OPERATION 2.1 INTRODUCTION This section provides a detailed analysis of the EXPANDORAM II board. It contains: FUNCTIONAL DESCRIPTION BOARD PARTS AND DESCRIPTION (Table 2-1) CIRCUIT ANALYSIS MEMORY UTILIZATION 2.2 FUNCTIONAL DESCRIPTION The major functions of the EXPANDORAM II board are shown in figure 2-1. The following functions make up the memory interface: Memory Array, memory decode and control, address multiplexer, data buffer, port address decode, and page select. 2.2.1 Memory Array The memory array consists of up to 32 dynamic random access memory elements (DRAM). Each element (chip) has a 65,536 by l bit capacity (64K). The 32 DRAMs are organized into four banks of eight DRAMs each. The eight DRAMs each contribute one bit to an addressable location. Each bank provides 65,536 Bytes. The total storage capacity of the EXPANDORAM II is 262,144 Bytes using 4 banks of 64K DRAMs. 2.2.2 Memory Decode and Control The memory decode and control circuitry is responsible for generating the timing signals for the memory array, address multiplexer, and data buffer. Timing within the memory decode and control circuitry is generated by a TTL compatible delay line. A 82S130 PROM is used to select the proper banks according to the address lines, board select switches, and the page number latch. (See Subsection 2.4.1 for more details on PROMs). 2.2.3 Address Multiplexer The address multiplexer is responsible for taking the address bits from the address bus buffers and multiplexing the proper row and column address into the memory array under control of the memory decode and control circuitry. 2.2.4 Data Buffers The data buffers isolate the memory array from the data bus controlled by the memory decode and control section. 2.2.5 Port Address Decode The port address decodes I/O port FF and latches 6 bits of data into the page number latch. 2.2.6 Page Select Page select is performed by the contents of the page number latch and decoded by the 82S130 PROM. 2.3 CIRCUIT ANALYSIS (Reference Schematic Appendix) Table 2-1 provides a functional description of major EXPANDORAM II board parts. The circuit analysis references parts by designator and is organized as follows: Port decode, phantom, refresh, read, write, wait states, and power. Table 2-1. EXPANDORAM II BOARD PARTS AND DESCRIPTION -------------------------------------------------------------- LOCATION DESCRIPTION -------------------------------------------------------------- U21 Flip Flop Wait State U13 Page Number Latch U19 Port FF Decoder U8, S3 Board Address Decode Logic (Determine which bank and board are enabled) U5, U1 Bank Enable Select U2 Column Address Select (Delay Line) U16 On-Board Refresh Counter U9, U14 Refresh Address Buffer U23 Lower Address Buffer U24 Upper Address Buffer U25 Data Input Buffer U20 Data Output Buffer U26-U50 RAM Matrix (4 x 8 Array) VR1, VR2 Power Supply Regulators 2.3.1 Port Decode The lower address buffer (U23) is monitored by a NAND gate (U19). When the address 0xFF is present on the lower address lines, the output of U19 becomes true (logic level low) and the signal FF* is inverted by U22 pin 8 and presented to pin 13 of U10. When Pin 1 of U7 is high (refresh not occurring or memory cycle not occurring), the output of U10 pin 11 conditions U7 pin 11 to monitor the input signal sOUT. sOUT is generated by the system Central Processing Unit (CPU) to indicate that a I/O data transfer bus cycle is underway. When the CPU drives sOUT and I/O address 0xFF on the S100 Bus U7 pin 13 becomes true (logic level high), latching the data from the Buffered Data Out bus onto the outputs of the page number latch U13. The CPU will have placed the required data pattern on the system Data Out bus. Because the data input buffer (U25) is always enabled, whatever data is on the system Data Out bus will also appear on the Buffered Data Out bus. The output data pattern latched in U13 provides part of the addressing (A2-A5) required by the bipolar PROM (U8) which outputs the correct RAM bank enable data pattern from programmed PROM memory. PROM address bits AO and Al are provided from system address bits A14 and A15 which are buffered and inverted by U18 pins 2 and 12. PROM address bits A6-A8 are derived from switches (S3) which a-re user selectable. Subsection 2.4 provides more information on switch settings and software partition of system memory. A successful port decode outputs a RAM bank enable data pattern from the PROM (U8) through the bank enable switches (83) to the row address strobe circuitry (U5 and Ul). Any RAM bank enable line that becomes true (logic level low) from the PROM will also generate a true condition at U4 pin 8. This signal will allow data from the RAM matrix to be latched on the outputs of the data output buffer (U20) during a read process. 2.3.2 Phantom The phantom signal from the CPU is used to disable all data output from the EXPANDORAM II by causing pin 10 of U3 to be a logic low. The output of U3 pin 8 staying high turns off the tri-state data output buffer (U20). The EXPANDORAM II is provided with a jumper which connects E9 to E10. Removal of the jumper disallows use of phantom by the CPU for turning off the individual EXPANDORAM II board. 2.3.3 Refresh Refresh is required by Dynamic RAM memory devices to maintain valid data stored in an internal memory cell. The EXPANDORAM II is designed to generate refresh cycles from internal timing circuitry or from an external command from the system CPU (Typically a Z80). The external refresh command NDEF (RFSH*) (pin 66) is inverted by U12 and inverted again by U7C. When the output of U7C pin 10 goes low, the falling edge triggers the one shot (U58) causing a negative going pulse to be output to pin 4 of the flip-flop U6A. The output of U6A pin 5 becomes high, conditioning the NAND gates of Ul to allow the RAM bank enables to become true for all RAS* signals to the RAM matrix. U7C pin 10 going low also goes to U5, placing a logic level high on the inputs of NAND gate U1, causing the RAS* signals to occur. At the-same time, the U7 pin 10 low signal is inverted by U11 pin 9 which inhibits port decode operations from occurring at U7 pin 3 and conditions the binary counter (U9 pin 1) to increment after refresh is completed. The U7 pin 10 low signal also inhibits CAS* from occurring at U10 pin 1 and turns off the upper address buffer (U24) at U10 pin 9. The U7 pin 10 low signal also turns off the lower address buffer (U23) at U17 pin 1 and turns on the refresh counter address buffer (U14). The refresh counter contents are gated onto the RAM address lines and a RAS* only refresh cycle is performed. If the system, in which the EXPANDORAM II is installed, is inactive, an internal decade counter (U16) will count system clock cycles (¢l, pin 24) buffered at U22 pin 10. The counter (U16) is loaded by a logic level low at pin 9, generated by any previous read, write, or refresh operation. After 10 system clock cycles, a logic level high is input to U17 pin 10 and the next clock cycle on U17 pin 9 places a logic level low on pin 10 of flip-flop U6. The flip-flop U6 will set, placing a logic level high on pin 8 of U7. This places a logic level low on U7 pin 10 which performs a refresh identical to the external refresh previously described. When pin 5 of flip-flop U6 is set during the refresh cycle, a logic level high is placed on pin 1 of the delay line (U2). One hundred nanoseconds later, on pin 4 of the delay line, a logic level high on pin 3 of U14 is inverted, conditioning the c1ock input pin 11 of f1ip-flop U6. After an additional 150 nanoseconds, pin 2 of the delay line goes high, which clears flip-flop U6 on pin 1 from NAND gate U10 pin 6. Pin 5 of flip-flop U6 goes low and 100 nanoseconds later, pin 4 of the delay line (U2) goes low, clocking pin 11 of flip-flop U6 which places a logic level low on pin 9 of U6. 2.3.4 Read A read process uses many of the same circuits previously described in Subsection 2.3.3, Refresh. After the CPU has stabilized a valid memory address on the address bus, a memory read command sMEMR (pin 47) is inverted and placed on pin 2 of U3. The logic level high from U3 pin 12 clocks a logic level high onto pin 5 of flip-flop U6. The delay line (U2) is sequenced with a high signal appearing on pin 12 in 50 nanoseconds, on pin 4 in 100 nanoseconds, and on pin 2 in 250 nanoseconds. At the time that flip-flop U6 pin 5 goes high, pin 10 of U7 is also high, since a refresh is not being serviced. Pin 10 of U7 being high conditions pin 1 of U17 to output a logic level low on pin 3 to enable the lower address buffer (U23). Pin 5 of flip-flop U6 also conditions U1 NAND gates to allow the PROM data pattern to pass through, enabling one of the RAS* signal lines to one of the DRAM banks. The row address strobe (RAS*) is implemented using the lower 8 bits of the system address bus. Fifty nanoseconds later, pin 12 of U2 delay line goes high which gates a logic level low from U10 pin 8 and enables the upper address buffer (U24) and disables the lower address buffer (U23). After another 50 nanoseconds, pin 4 of U2 goes high which generates a column address strobe (CAS*) at pin 3 of U10. The CAS* is implemented using the enabled upper 8 bits of the system address bus. The 50 nanosecond delay allows the upper 8 bits of the address lines to stabilize before the CAS* strobe occurs. When pin 12 of the delay line U2 went high, turning on the upper address buffer, the same enable signal (U10 pin 8) also enabled the DIX data output buffer (U20). Since CAS* is still to be processed at this time, the data from the RAM matrix (pin 14) is unstable. The memory data is not latched until 250 nanoseconds later when U10 pin 6 goes low, resetting flip-flop U6 pin 5, which causes pin 12 of the U2 delay line to go low, latching the output data buffer with a logic level low on U20 pin 11. The addressed data in DRAM memory is output from the output data latch (U20) when the CPU inputs a pDBIN command (pin 78) which is inverted and gates a logic level high from pin 4 of U7 which enables a logic level low from pin 8 of U3 which turns on the output data buffer (U20) on pin 1. 2.3.5 Write A write process is almost identical to a read process and uses most of the timing circuits employed by a read process. After the CPU has stabilized a valid memory address on the address bus and a valid data pattern on the Data Out data bus, a memory write command, MWRT (pin 68) is inverted by U12 pin 12 and placed on pin 13 of U3. The logic level high from U3 pin 12 clocks a logic level high onto pin 5 of flip-flop U6. The DRAM RAS* and CAS* sequencing is then identical to a read cycle previously described except that the write command on pin 3 of all RAMs in the RAM matrix is held low by U3 pin 6. The data from the data input buffer (U25) is written into memory. Note that, since the data input buffer is always enabled (pins 1 and 19), the system CPU has all responsibility for valid data being stabilized on the Data Out data bus. 2.3.6 Wait States When the EXPANDORAM II is used with higher speed CPU boards (4 MHz or greater), a jumper must be installed connecting E14 to E15. The jumper allows the CPU bus status signal sM1 (pin 44) to initiate a wait state. The CPU will a1ways make sMl high when the CPU is executing an OP CODE fetch bus cycle. A logic level high on S-100 pin 44 is inverted by U12 which places a logic level low on pin 8 of U12. The logic level low is clocked through flip-flop U21 pin 5 to U11 pin 15 which enables a logic level low output from U11 pin 13 to S-100 pin 72, RDY command. This output will cause the CPU to execute a wait state cycle. The next bus clock cycle will pre-set flip-flop U21 with a logic level low from pin 9 which forces pin 5 high. Pin 5 at a logic level high will disable U11 pin 13 output which returns the RDY command to a logic level high. In systems configured with earlier SDSystems CPU boards (SBC200), when the RDY command is pulled low, an "ECHO" signal from the CPU is placed on pin 27 of the S-100 bus called pWAIT. This signal input on the EXPANDORAM II board prevents the on-board refresh counter (U16) from being accidentally halted by a POC* command occurring during a wait state. A pWAIT command disables NAND gate U17 pin 12. 2.3.7 Power Power for logic is derived from an on-board regulator (VRl) and decoup1ed by a series of capacitors. The S-100 bus provides unregulated +8 VDC on pins 1 and 51 and ground reference on pins 50 and 100. 2.4 MEMORY UTILIZATION The EXPANDORAM II board has been integrated into computer systems which operate on the following software operating systems: CP/M MP/M COSMOS OASIS For the memory on the EXPANDORAM II to be utilized correctly, a Programmable Read Only Memory (PROM) (U8) is installed on each board with a SDSystems program written to optimize the memory partitioning required by the operating systems previously mentioned. Specific switch settings and strapping are also required to allow the EXPANDORAM II to function correctly. 2.4.1 Programmable Read Only Memory (PROM) The U8 82S130 PROM shipped with the EXPANDORAM II board is designed for operating systems which utilize a 48K memory partition per page. A page of memory is typically reserved for each user in the operating system memory allocation. A page number (0-9) is then equivalent to a user number (0-9). The PROM has 9 address lines (A0-A8) which are divided into three fields: S (Board Number), P (User Number), and A (Address) (reference Figure 2-2). The S field address bits A6-A8 are developed from the S3 switch settings which provide this EXPANDORAM II board number and a PROM enable. The P field address bits A2-A5 are developed by the system CPU and latched into U13 during a port (FF) decode cycle. The P field is the page or user number. The A·field address bits A0-A1 are provided by the system CPU on the two upper system address bits A14 and A15. The A field is the RAM bank number. The PROM has 6 output data lines which are utilized in the EXPANDORAM II. Four output data bits are used to enable 1 of the 4 DRAM banks in the matrix. The remaining 2 output data bits become address bits A14-A15 in the upper address buffer. Figure 2-2 depicts the page-bank-board map of a typical operating system using 10 48K pages on two EXPANDORAM II boards. 2.4.2 Switch Settings And Strapping Switch settings information on S3 for the EXPANDORAM II is given in Figure 2-3. Factory setting is all switches ON. I/O Port 0xFF is used to select the memory page to be accessed by the CPU. Up to 10 pages (0-9) are supported, using either 6 boards with 32K page PROMs or 8 boards with 48K page PROMs (User 0xA has 16KB located @ 0xC000). Mixing page sizes between boards is not supported. The pages are accessed by outputing the page number to port 0xFF. Switch S3 8 - PROM Enable (Must be On) 7 - D0 (Board Select On = 0, Off = 1) 6 - D1 (Board Select On = 0, Off = 1) 5 - D2 (Board Select On = 0, Off = 1) 4 - B0 (Bank Enable - On) 3 - B1 (Bank Enable - On) 2 - B2 (Bank Enable - On) 1 - B3 (Bank Enable - On) Two straps are factory installed: E9-E10 and E14-E15. These straps are required for most SDSystems configurations and software. The E9-E10 jumper strap is used for phantom operation and E14-E15 is used to generate wait states during certain CPU operations. 2.4.3 EXPANDORAM II In Non-SDSystems Environments The EXPANDORAM II provides several "jumper" pads for altering the board to operate in a non-SDSystems environment. The board is manufactured with these jumpers connected by etch for operation with SDSystems CPU boards. These jumpers can be modified to operate with other CPU boards. NOTE: These modifications probably will require modification of both on-board firmware and system software for correct operation. 2.4.3.1 Jumper Pads E22, E23, and E24 (Clock Source) (Rev D, E) These jumpers provide for selection of the S-100 bus pin upon which system clock is received. The board is etched for reception of phase one (Ol) clock on pin 24 of the S-100 bus. This is an IEEE-696 signal. The jumper can be changed by cutting the etch between E23 and E24 and installing a jumper between E22 and E23. This enables reception of the system clock on S-100 pin 25. NOTE: This is not supported by IEEE-696. The IEEE-696 signal on pin 25 is pSTVAL. 2.4.3.2 Jumper Pads E25, E26, and E27 (Reset Source) (Rev D, E) The jumper pads E25, E26, and E27 provide for se1ection between Power On Clear (POC) (S-100 pin 99) or RESET (S-100 pin 75) as the board reset signal. This allows the capability to reset the EXPANDORAM II by use of the RESET signal. Since RESET is asserted concurrently with POC, this will not affect power up reset. NOTE: The IEEE-696 signal RESET is to reset bus masters; however, the EXPANDORAM II board is a permanent bus slave. The board is etched to use POC. To use RESET: Cut the etch between E25 and E26 and install a jumper between E26 and E27. 2.4.3.3 Jumper Pads E16, E17, and E18 The jumper pads E16, E17, and E18 are initially configured such that address line A14 is supplied by the page decode logic (PROM U8 - pin 11). This can be jumpered such that A14 is tied to S-100 bus address line A7. This can be accomplished by cutting the etch between E17 and E18 and attaching a jumper between E17 and E16. NOTE: This may require firmware modification. 2.4.3.4 Jumper Pads E19, E20, and E21 (Rev D, E) The jumper pads E19, E20, and E2l allow the most significant bit of the page decode logic (PROM U8 - pin 16) to be tied to A13* (inverted S-100 bus address line A13). The initial configuration of these jumpers has this most significant bit of the page decode logic tied to the port decode latch U13 pin 10. The modification to use A13* in PROM addressing can be accomplished by cutting the etch between E19 and E20 and attaching a jumper between E20 and E21. NOTE: This may require firmware alteration. 2.4.3.5 Jumper Pads E6, E7, and E8 (RAM Type) 2.4.3.5A Jumper Pads E4 and E5 (RAM Type) 2.4.3.5B Jumper Pads E1, E2, and E3 (RAM Type) The jumper pads E6, E7, and E8 configure the source for DRAM pin 9. Either address bit A7 of the RAM matrix (64) or tied to +5V (16). This allows selection of 64KB or 16KB per DRAM bank. This can be accomplished by cutting the etch between E6 and E8 (16) and attaching a jumper between E6 and E7 (64). The jumper pads E4 and E5 configure if DRAM pin 1 is connected to -5V (16) or open (64). This can be accomplished by cutting the etch between E4 and E5 (-5V). The jumper pads E1, E2, and E3 configure which voltage DRAM pin 8 is tied to, either +5V (64) or +12V (16). This can be accomplished by cutting the etch between E1 and E2 (+12V) and attaching a jumper between E2 and E3 (+5V). 2.4.3.6 Jumper Pads E9 and E10 (Phantom Memory Operation) The jumper pads E9 and E10 are initially configured to enable the use of Phantom Memory Operation by monitoring S-100 Pin 67 and disabling the output data buffer U20 when low. 2.4.3.7 Jumper Pads E14 and E15 (Wait State Operation) The jumper pads E14 and E15 are initially configured to enable the generation of wait states by pulling S-100 RDY Pin 72 low during certain CPU operations.